As integrated circuits have become increasingly miniaturized, the need to provide low resistance and highly reliable device interconnections has become more critical. Much attention has been placed upon improving the metallurgical contacts which interconnect metallic circuit nodes and doped semiconductor regions of integrated circuit devices.
A considerable effort has been geared towards developing interconnections and associated manufacturing processes which include the use of tungsten filled contacts. Tungsten is a refractory metal having a low resistance and relatively high temperature stability which makes its use attractive. The development of improved selective chemical vapor phase deposition (CVD) processes has made tungsten a prime candidate to replace the metal silicides conventionally used in interdevice contacts.
When tungsten (W) is used to fill via holes that extend to semiconductor device impurity regions, it is customary to include a barrier layer such as titanium (Ti) or titanium nitride (TiN) between the tungsten and the semiconductor material. The barrier layer enhances adhesion and lowers the contact resistance between the tungsten layers and the impurity regions. A TiN layer may be deposited, for example, by sputtering prior to tungsten deposition by low pressure CVD, sputtering or electron beam evaporation.
While the advantages of tungsten are thus well established, especially in providing low contact resistance interconnects, it has a relatively high sheet resistance in comparison to other metals, such as aluminum (Al). In device interconnects having long current paths, it is therefore advantageous to include aluminum for lowering the interconnect resistance. Now, it is well known that it is poor practice to directly form metals such as aluminum on impurity diffusion regions in a silicon substrate. This results in alloy spikes and/or silicon nodules produced by reaction between aluminum and silicon due to thermal hysteresis. To prevent these problems, it is known to use a barrier metal layer such as Ti and/or TiN between the aluminum and the silicon substrate. Also, a Ti or TiN barrier layer is used to prevent direct aluminum contact with dielectrics such as silicon dioxide (SiO.sub.2) used as isolators within the integrated circuit. However, a problem in the manufacture of interconnects using aluminum with Ti and/or TiN is that oxidation of the aluminum often occurs in the interface between the aluminum and barrier layers or between the aluminum and tungsten layers. This oxidation significantly increases the contact resistance of the Al/barrier layers or Ae/w layers and lowers the reliability of the contact.
A prior art interconnect structure including both tungsten and aluminum layers, and formed from a "dual damascene" process is shown in FIG. 1. The dual damascene process referred to herein is a process in which a metallic "runner" layer along with via hole conductive fillers are formed in one process step. The via holes extend down to conductive regions of the integrated circuit which are to be electrically connected by the interconnect. The runner layer connects the via hole conductive fillers to couple the conductive regions of the circuit. Since the conductive regions may be a relatively considerable distance away from each other, it is desirable that the runner layer be comprised of a metal with a low sheet resistance such as aluminum.
In FIG. 1, via holes 24, 26 and a runner opening 28 are first formed within an insulating body 16 such as silicon dioxide (SiO.sub.2). The via holes 24 and 26 are shown to extend down to tungsten contact regions 14 and 15. Barrier layers 13 and 17, such as Ti and/or TiN, separate tungsten contact regions 14 and 15 from impurity regions 19 and 21 (which are formed within a silicon substrate 25). In the dual damascene process, via holes 24 and 26 and runner opening 28 are simultaneously filled with conductive material in one process step. A Ti and/or TiN barrier layer 22 is first applied within openings 28, 24 and 26. Aluminum layers 20 are then formed over barrier layer 22 by sputtering. Another barrier layer 25 is deposited over the aluminum layers 20. Finally, a thick tungsten layer 12 is applied to fill the remainder of the via hole openings 24, 26 and runner opening 28. This tungsten layer 12 thus encapsulates the aluminum layers, thereby providing a high reliability configuration in the metallic runner region. In the resulting configuration the current that flows between conductive regions 19 and 17 generally flows in the vicinity of current path 31. It is seen that a substantial portion of current path 31 is within the aluminum layers 20 such that a low sheet resistance is provided.
However, a shortcoming of the FIG. 1 interconnection configuration is that the current has to flow through many critical interfaces. As shown, current path 31 crosses aluminum/barrier layer interfaces 27, 23, 30 and 18, and runs along interface 29. These interfaces are prone to oxidation problems, resulting in potentially poor contact resistance and a high interconnection failure rate.
Accordingly, it is an object of the present invention to provide an integrated circuit interconnection which has improved contact resistance and higher reliability while also having a low sheet resistance.
It is a further object of the present invention to provide a dual damascene process to fabricate an improved integrated circuit interconnection.
These and other objects and advantages of the present invention will become apparent to those of ordinary skill in the art having reference to the following detailed description of an exemplary embodiment thereof.